The present invention relates to cell library databases used in computer-aided design (CAD) for logic circuits such as semiconductor integrated circuits and design aiding systems employing this database. Particularly, the present invention relates to cell library databases and timing verification and withstand voltage verification systems of integrated circuits which are appropriate for logical verification, timing verification of delay or the like, failure analysis, and logical verification used in a software development tool.
Generally, computer-aided design (CAD) for a logic circuit such as a semiconductor integrated circuit has conventionally adopted, as a cell library database used for the CAD, a database structure which includes a symbol as shown in FIG. 7A, logical information as shown in FIG. 7B, and logic delay information as shown in FIG. 7C. The symbol shown in FIG. 7A is a logic component indicating a logical product (referred hereinafter to as a NAND gate). FIG. 7B lists logical information on the input-output relation of the NAND gate, and FIG. 7C lists information on logic delay occurring between the change of an input signal and the change of an output signal. Logic design of a semiconductor integrated circuit composed of various types of gates generally conducts logic verification according to the truth table in FIG. 7B and timing verification for checking, with the logic delay information as shown in FIG. 7C, whether the total of logic delays is within a predetermined period of time.
In recent years, a decrease in the threshold voltage of a transistor of a semiconductor integrated circuit accompanied with miniaturization of the circuit, however, has caused a big problem of an increase in leakage current during standby. To solve this problem, a technique for reducing power consumption during standby has conventionally been proposed in which leakage current from the power source is eliminated by stopping power supply during standby. In conducting logical verification on a semiconductor integrated circuit employing this technique in which the power supply is started and stopped, employment of the library database structure in FIG. 7 causes the following problems. First, even when power is not supplied to the circuit, a logic output is produced according to the truth table in FIG. 7B. This prevents a total logical verification including a power control thereof. Second, though the logic delay time between input and output signals at start up of the power source is different from the delay time between input and output signals under normal operation, the database only contains delay time information in the condition in which a steady power is supplied. This prevents an accurate timing verification in consideration of the delay time between the input and output signals at the start up of the power source.
To deal with the foregoing problems, the inventors proposed, in Japanese Unexamined Patent Publication No.2000-305961, a database structure as described below. In this database structure, the database of each cell library contains information on a power source as input information, and logics produced by voltage information of this source and different pieces of input signal information constitute this structure. This structure will now be discussed briefly using FIG. 8. FIG. 8A shows a symbol for a NAND gate. As compared with the symbol of FIG. 7A, that of FIG. 8A has in addition input information V of the source. As shown in FIG. 8B, logical information including source voltage information V is databased so that a source V of L (no-supply) produces an output Y of X (undefined). As compared with the logic delay information of FIG. 7C, that of FIG. 8C has in addition delay times VYns when the source voltage information V is changed. The cell library database proposed by the inventors contains the logical information according to on/off information of the source and information on logic delays of the output Y produced by changing power supplied, so that the database enables logic and timing verifications of the semiconductor integrated circuit using the technique in which the power supply is started and stopped.
Due to the needs for a further reduction in power consumption of a semiconductor integrated circuit, variable power supply techniques have recently been proposed which are intended for the circuit operation with lower power consumption by dynamically changing the source voltage and operation frequency (clock frequency) even when the circuit is in operation.
In conducting logical or timing verification on a semiconductor integrated circuit to which the above technique is applied, the database structure proposed by the inventors causes the following problems. Though logic delay information of a cell library generally varies according to the source voltage value thereof, it only contains, as shown in FIG. 8C, delay information of a single source voltage value and cannot hold the information of the source voltage value in the form of logical information. This prevents timing verification according to a dynamic change in the source voltage value. Moreover, the variable power supply technique described above may supply different source voltages to the circuit, which causes the need for verifying withstand voltage of every cell library.